The Storage and Memory Signal

Direction: Worsening.

This period: Michael Dell told CNBC this week that the shortage "gets worse next year" and could be a four-year problem, the most direct demand-side read yet on how long buyers expect this to run. Micron backed that up on October 15, opening a second HBM packaging plant in Taichung, Taiwan, where President and COO Manish Bhatia said the site's entire planned 2027 output is already sold out, a step up from the "more than three-quarters committed" figure disclosed on last month's earnings call. Working the other side of the same equation, Digitimes reported October 14 that SK hynix is pushing some HBM4 back-end equipment originally due this year into 2027, with at least part of the freed-up line reportedly going to conventional DDR5 instead, a reminder that the HBM-versus-DRAM tradeoff this newsletter has tracked since Issue 03 can cut either direction depending on which tool shows up on schedule. And China's CXMT said October 10 it has made progress on a 4F² DRAM cell roughly a third smaller than the 6F² design Samsung and SK hynix use today, with DDR5 RDIMM modules targeted before year end, a claim that knocked both companies' shares down on October 13 even though Samsung isn't expected to reach 4F² production until 2028 and Citi calls CXMT four generations behind on process maturity.

Driver: Unchanged since Issue 03: HBM production still eats disproportionately into capacity that would otherwise make conventional DRAM. Micron's new plant and Dell's own language both point to that squeeze extending through 2027 and beyond, rather than easing next year the way some buyers had hoped.

Watch for: An earnings gauntlet starting October 21 with IBM, then Western Digital on October 22, then the October 26-30 stretch with Rambus, SK hynix, Seagate, Samsung, and Kioxia, the first chance to hear whether any of this week's reported figures, Micron's sold-out claim, Dell's four-year estimate, CXMT's roadmap threat, show up in anyone else's own guidance language.

The OCP Global Summit ran October 12-15 at the San Jose McEnery Convention Center, the last edition before it relocates to San Francisco's Moscone Center for 2027, and this newsletter already flagged the headline keynotes and CXL memory demos in Issue 11's preview. What showed up on the actual floor was narrower and more interesting than a generic AI-infrastructure trade show: a genuine wave of co-packaged optics products, all aimed at the same physics problem this newsletter's Issue 11 Uplevel Highlight described, copper running out of room once a cluster gets big enough.

Astera Labs led with two separate announcements. Aries 7, unveiled October 13, is what the company calls the industry's first PCIe 7 signal-conditioning portfolio spanning copper and optical interconnects: smart retimers, smart redrivers, smart cable modules, and smart optical driver and TIA chips, covering everything from chip-to-chip links to rack-to-rack connections stretching more than 50 meters over fiber. Sampling is targeted for the fourth quarter to select hyperscale and OEM customers. A day earlier, Astera Labs showed Orion, a compute-agnostic, rack-scale reference architecture meant to let customers mix GPU and CPU vendors inside the same AI factory design rather than committing to one supplier's full stack. Credo Technology answered with its own October 12 launch: a 1.6T ZeroFlap Active Light Cable, which the company bills as the industry's first row-scale, wide-parallel optical interconnect, drawing about 12 watts per cable end, roughly 30% less power than a comparable active electrical cable, at a tenth the weight and a 50-meter reach. Lightmatter and contract manufacturer Flex went further still, unveiling co-packaged optics switch trays, a 204.8 Tbps design and a 102.4 Tbps design built around Lightmatter's own laser and optics technology, the first systems to put that combination inside OCP's open rack form factors.

The switching silicon underneath all of this is why the optics push isn't optional. Marvell showed Teralynx T100, a 102.4 Tbps switch built on 3nm silicon with on-chip telemetry and congestion control tuned for the bursty, collective traffic patterns of AI training, alongside its Structera line of CXL memory expansion and acceleration chips. Broadcom demoed its Tomahawk 6 and Jericho 4 switches at the same bandwidth class. Celestica introduced the DS6005, a 102.4 Tbps, fully liquid-cooled switch built around co-packaged optics specifically to cut the power overhead of moving that much data through pluggable modules. None of these chips exist because engineers wanted a bigger number on a spec sheet. They exist because the electrical signal integrity problem this newsletter has tracked since covering silicon photonics last issue gets worse, not better, every time rack-to-rack bandwidth doubles.

The memory-fabric half of the show was smaller but arguably more relevant to this newsletter's core beat. SK hynix's second-generation CMM-DDR5 CXL module, covered in this issue's Signal section and Vendor Tracker, is a direct descendant of the CXL memory pooling concept this newsletter explained back in Issue 03, now shipping as a 256GB, 80GB/s product rather than a slide. Unifabrix demonstrated a large-capacity CXL Composable Memory System in OCP's Innovation Village, extending pooled memory toward computational-memory and offload functions rather than treating it as pure capacity. Baya Systems showed a high-radix network-on-chip switching architecture aimed at the chiplet era, where a single accelerator package is itself built from multiple dies that need their own internal fabric. And in a live demo that got less attention than the big switch announcements, Wiwynn, Ayar Labs, and GUC showed an integrated optical compute system combining a Wiwynn chassis, a GUC ASIC, and Ayar Labs' TeraPHY optical engine, with real-time telemetry proving the optical link stayed up inside a running chassis rather than just on a lab bench.

Put together, the show's real theme wasn't any single product. It was an entire industry simultaneously concluding that the rack is no longer the right unit of memory and compute, and that connecting racks to each other at the bandwidth AI training now demands requires replacing copper with light well before anyone expected to need it. Nvidia's decision to open its Vera Rubin NVL72 rack and compute-tray designs through MGX 1.2, built for 250kW of rack power, is the blunt instrument version of the same point: if a single rack is going to draw a quarter-megawatt, the interconnect inside and around it has to stop losing power to copper's own resistance.

CoreWeave's bonds slid into distressed territory the week of October 14-17, with its 2031 notes trading as low as the high 70s cents on the dollar and yields on that paper pushing above 16%. The company's five-year credit default swap spread jumped as much as 74.5 basis points in a single session on October 15 to a record intraday high of 1,194.5 basis points, meaning it would cost roughly $119,500 a year to insure $1 million of CoreWeave debt. Different trackers put the implied five-year default probability embedded in that pricing anywhere from just over 60% to as high as 64%, a sizable range but not a flattering one in either direction. CoreWeave shares fell 11.2% on October 16. The proximate trigger, per multiple reports, was fresh news that the company plans to borrow even more to fund GPU infrastructure, on top of roughly $52 billion in existing loan and lease obligations, right as its net interest expense more than doubled year over year to $640 million.

Nvidia's Jensen Huang pushed back publicly the same day the CDS spread hit its record, telling Bloomberg that CoreWeave's financing costs are falling, not rising, and that there's no need for Nvidia to step in as a backstop. ARK Invest's Cathie Wood bought CoreWeave shares on both October 14 and October 15, buying into the selloff rather than away from it. Whether that's conviction or just ARK's usual approach to volatility is a separate question; the fact that both Nvidia's CEO and a prominent public investor felt the need to say something at all is itself a signal that the market's doubts registered.

The contagion reached further than CoreWeave's own cap table. Backblaze shares fell 22.26% on October 14 as AI-infrastructure names sold off broadly, a drop tied specifically to coverage of Backblaze's reported $335 million CoreWeave-linked deal and the funding risk that exposure now implies. That's a cloud storage vendor, not a GPU cloud, getting hit on balance-sheet proximity to a single customer's credit stress, which is exactly the kind of second-order risk this newsletter doesn't usually have reason to flag.

None of this means CoreWeave is going to miss a payment. Huang's comments and Wood's buying both point toward people close to the company believing the financing will hold. But every figure in this issue about HBM capacity being sold out, DRAM pricing resets, and multi-year shortages rests on an assumption that keeps getting treated as background noise: that the neoclouds and hyperscalers signing those long-term memory commitments can actually keep paying for the compute those chips go into. CoreWeave's bond market just put a number on how confident outsiders currently are in that assumption, and it isn't a comfortable one.